This invention relates to junction field effect transistors and more specifically to junction field effect transistors having a subsurface gate structure.
Junction field effect transistors ("JFETs") are well known in the art. Examples of JFETs are discussed in U.S. Pat. No. 4,543,706, issued to Bencuya et al., and U.S. Pat. No. 4,476,622, issued to Cogan, each incorporated herein by reference. In the processes discussed in the '622 and '706 patents, an N- epitaxial layer 1 is grown on an N+ substrate 2 and an N+ region 3 is formed at the surface of N- epitaxial layer 1 (FIG. 1). N+ substrate 2 serves as the JFET drain, and N+ region 3 at the epitaxial layer surface serves as the source. Grooves 4 are etched into epitaxial layer 1, silicon dioxide layers 5 are grown on the vertical walls of grooves 4, and P type impurities are implanted and diffused into the semiconductor material at the bottom of grooves 4, thereby forming P type gate regions 6. A metal layer 7 is then deposited at the bottom of the grooves 4 to electrically contact P type gate regions 6. (In the '706 patent, grooves 4 are filled with a solid inert material so that the resulting structure has a planar surface.)
The size of the depletion regions 8 between P type gate regions 6 and N- epitaxial layer 1 is controlled by applying a selected voltage to gate regions 6 via metal layer 7, thereby controlling the amount of curent flowing between N+region 3 and substrate 2.
A variation of the above-described vertical JFETs is discussed in U.S. Pat. No. 4,566,172, issued to Bencuya et al., in which the P type gate regions extend from the sides of the grooves but not beneath the grooves. This results in reduced gate capacitance.
Another variation of a process for forming a vertical JFET is discussed in U.S. Pat. No. 4,375,124, issued to Cogan, in which the P type gate region is formed by diffusing impurities from P doped polysilicon deposited in the grooves into the epitaxial layer. The '172 and '124 patents are incorporated herein by reference.